[Python] python myhdl package how to generate verilog initial block

From the code mostly from the sample of myhdl:

from myhdl import Signal, intbv, delay, always, now, Simulation, toVerilog

__debug = True

def ClkDriver(clk):
halfPeriod = delay(10)
@always(halfPeriod)
def driveClk():
clk.next = not clk
return driveClk

def HelloWorld(clk, outs):

counts = intbv(3)[32:]

@always(clk.posedge)
def sayHello():
outs.next = not outs
if counts >= 3 - 1:
counts.next = 0
else:
counts.next = counts + 1
if __debug__:
print "%s Hello World! outs %s %s" % (
now(), str(outs), str(outs.next))

return sayHello

clk = Signal(bool(0))
outs = Signal(intbv(0)[1:])
clkdriver_inst = ClkDriver(clk)
hello_inst = toVerilog(HelloWorld, clk, outs)
sim = Simulation(clkdriver_inst, hello_inst)
sim.run(150)


I expect it to generate a verilog program that contains an initial block, like something:

module HelloWorld(...)
reg [31:0] counts;
initial begin
counts = 32'h3
end
always @(...


How can you get the initial block generated?

Note that on the google cache for old.myhdl.org/doku.php/dev:initial_values it links to example https://bitbucket.org/cfelton/examples/src/tip/ramrom/ . So it looks the feature should be supported. However the rom sample generates static case statements. That's not what I'm looking for.

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